The present invention relates to a semiconductor device including a semiconductor substrate with stepwise differences on the upper surface thereof, and a method for fabricating the semiconductor device.
Semiconductor devices of high integration, such as LSIs, VLSIs, etc., generally have the so-called multi-wiring layer structure having an n-th wiring layer formed by providing a wiring in a layer on a substrate, and further an n+1-th wiring layer formed through an insulating layer.
Insulating layers, or inter-layer insulating layers, included in such multi-wiring layer structure have the intrinsic purpose of securing insulation between upper and lower layers (between a substrate and a wiring layer or between wiring layers), and in addition the purpose of covering smoothly the rough substrate or wiring layers having stepwise differences on the upper surface thereof for planarization.
That is, as integration of semiconductor integrated circuits are improved, steps on surfaces of formed devices are large, and wires have to be thickened in compensation for lowered wiring capacities due to micronization of wiring. Taking it into consideration that steps resulting from a wiring tend to be larger, it is necessary to ensure planarization of inter-film insulating films in forming multi-layer wirings.
This is because, if an inter-layer insulating film adversely permits roughness of a lower layer (a substrate or a lower wiring layer) to be still present in an upper layer, there is a risk that breakage and defective insulation will be caused to a wiring of the upper layer, and a margin of a focal depth of a resist in the wiring will be adversely narrowed, and integration of the wiring may be impaired.
The conventional methods for forming an inter-layer insulating film includes a method (a) for forming an SiO.sub.2 film on the surface of a substrate by CVD using a compound gas, such as SiH.sub.4 or others, a method (b) for forming a CVD film using ozone-TEOS (tetraethoxy silane), a method (c) for forming an SOG (spin on glass) film by solving SiO.sub.x in a solvent, such as alcohol or others, and applying the SiO.sub.x to the surface of a substrate, and other methods.
But in the method (a), roughness of a wiring itself is still present in an upper layer. A problem with the method (a) is that a formed inter-layer insulating film has very poor planarization.
In the above-described methods (b) and (c), roughness in a region with small inter-wire gaps can be planarized by reflow, but steps (global steps) between regions without wirings formed or plane electrode layers such as ground electrode or power electrode layers, and regions with fine wirings formed dense can not be eliminated. This is a problem with the methods (b) and (c).